Layout for dut arrays used in semiconductor wafer testing

ABSTRACT

A layout for devices under test formed on a semiconductor wafer for use in wafer testing includes a first array of devices under test and a first pad set formed adjacent to the first array. The first pad set includes a gate force pad, a source pad, and a drain pad. Each of the devices under test in the first array is connected to the gate pad of the first pad set. Each of the devices under test in the first array is connected to the source pad of the first pad set. Each of the devices under test in the first array is connected to the drain pad of the first pad set.

CROSS REFERENCE TO RELATED APPLICATION

The present application is a Continuation of U.S. application Ser. No.11/243,016, filed on Oct. 3, 2005, issued as U.S. Pat. No. 7,489,151,which is incorporated herein by reference in its entirety for allpurposes.

BACKGROUND

1. Field:

The present application generally relates to device under test (DUT)arrays, and, more particularly, to a layout for DUT arrays used insemiconductor wafer level testing.

2. Description of Related Art

To assist in evaluating and/or controlling a semiconductor fabricationprocess, integrated circuit devices are fabricated on a wafer as testdevices. These test devices are referred to as devices under test(DUTs). Typically, a wafer with DUTs formed thereon is positioned withina wafer tester. The wafer tester has an array of probes that makeelectrical contact with contact pads for the DUTs on the wafer. Thewafer tester then performs electrical testing of the DUTs.

Typically, each DUT on a wafer has one or more contact pads assigned toit. Thus, in order to test all the DUTs on the wafer, the wafer testerhas to either have enough probes to make contact with all the contactpads of all the DUTs on the wafer or test groups of DUTs at a time.Thus, the number of DUTs on a wafer can be limited by the number of DUTsthat can be tested within a reasonable amount of time using the wafertester.

A variety of arrays of DUTs are in use today. For example, a CMOS devicearray for determining the variability of the drive current is disclosedin Ohkawa, S., Aoki, M., Masuda, H., “Analysis and Characterization ofDevice Variations in an LSI Chip Using an Integrated Device MatrixArray”, Proc. International Conference on Microelectronic TestStructures (ICMTS), pp 70-75, 2003, which is incorporated by referenceherein. However, in this array, the DUTs are measured in sequence, whichis very slow. Also, device parameters like the threshold voltage cannotbe measured due to the large array size. Furthermore, this approachcannot be ported into a scribe line.

Another array of various DUTs is disclosed in Leffers, R., Jakubiec, A.,“An Integrated Test Chip for the Complete Characterization andMonitoring of a 0.25 um CMOS Technology that fits into five scribe linestructures 150 um by 5000 um”, Proc. International Conference onMicroelectronic Test Structures (ICMTS), pp 59-63, 2003, which isincorporated by reference herein. This array, however, requires acustomized probe card with an operational amplifier connected to certainpins. Additionally, all measurements are done in sequence and there areforce and sense pads required for both source and drain.

Another array of CMOS devices is disclosed in Quarantelli, M., Saxena,S., Dragone, N., Babcock, J. A., Hess, C., Minehane, S., Winters, S.,Chen, J., Karbasi, H., Guardiani, C., “Characterization and Modeling ofMOSFET Mismatch of a Deep Submicron Technology”, Proc. InternationalConference on Microelectronic Test Structures (ICMTS), Monterey (USA),2003, which is incorporated by reference herein. In this array, thereare selection devices on the drain path, which increases routingresistance significantly, and there will be a noticeable voltage drop ifmultiple devices are measured in parallel to save test time. Similarlimitations exist for the CMOS device array disclosed in Saxena, S.,Minehane, S., Cheng, J., Sengupta, M., Hess, C., Quarantelli, M.,Kramer, G. M., Redford, M., “Test Structures and Analysis Techniques forEstimation of the Impact of Layout on MOSFET Performance andVariability”, Proc. International Conference on Microelectronic TestStructures (ICMTS), Hyogo (Japan), 2004, which is incorporated byreference herein. Additionally, these arrays do not fit into a scribeline, as may be desired.

An array of bipolar devices is disclosed in Einfeld, J., Schaper, U.,Kollmer, U., Nelle, P., Englisch, J., Stecher, M., “A New Test Circuitfor the Matching Characterization of npn Bipolar Transistors”, Proc.International Conference on Microelectronic Test Structures (ICMTS),Hyogo (Japan), 2004, which is incorporated by reference herein. In thisarray, there are selection devices to all DUT pins (in this case base,emitter and collector) and measurements are executed in sequence, whichis a slow process.

Another array of CMOS used to determine parameter variation of devicesis disclosed in Schaper, U., Einfeld, J., Sauerbrey, A., “ParameterVariation on Chip Level”, Proc. International Conference onMicroelectronic Test Structures (ICMTS), pp 155-158, 2005, which isincorporated by reference herein. In this array, each transistor isaddressed by a decoder and measured individually in sequence.

In addition, there are also SRAM or ROM based arrays disclosed inDeBord, J. R. D., Grice, T., Garcia, R., Yeric, G., Cohen, E., Sutandi,A., Garcia, J., Green, G., “Infrastructure for Successful BEOLCharacterization and Yield Ramp at the 65 nm Node and Below, Proc. IITC2005, which is incorporated by reference herein. These arrays, however,are not used to extract variation of device related parameters likedrive current or threshold voltage.

SUMMARY

In one exemplary embodiment, a layout for devices under test formed on asemiconductor wafer for wafer testing includes a first array of devicesunder test and a first pad set formed adjacent to the first array. Thefirst pad set includes a gate force pad, a source pad, and a drain pad.Each of the devices under test in the first array is connected to thegate pad of the first pad set. Each of the devices under test in thefirst array is connected to the source pad of the first pad set. Each ofthe devices under test in the first array is connected to the drain padof the first pad set.

DESCRIPTION OF DRAWING FIGURES

The present application can be best understood by reference to thefollowing description taken in conjunction with the accompanying drawingfigures, in which like parts may be referred to by like numerals:

FIG. 1 depicts an exemplary layout of devices under test in accordancewith one exemplary embodiment;

FIG. 2-A depicts another exemplary layout of devices under test inaccordance with another exemplary embodiment;

FIG. 2-B depicts a cross-sectional side view of FIG. 2-A;

FIG. 3 depicts an exemplary addressing and routing scheme for an arrayof devices under test;

FIG. 4 depicts an exemplary core structure for a device under test;

FIGS. 5-A and 5-B depict exemplary routing connections for a deviceunder test;

FIG. 6 depicts exemplary tree routing structures for devices under test;

FIG. 7 depicts rows of devices under test connected to tree routingstructures;

FIG. 8 depicts an exemplary pad frame in accordance with an exemplaryembodiment;

FIG. 9 depicts a portion of the pad frame depicted in FIG. 8;

FIG. 10 depicts a cross section of FIG. 9; and

FIG. 11 depicts an exemplary pad mapping of a pad frame.

DETAILED DESCRIPTION

Devices and/or structures may be described herein using absolute and/orrelative directions and orientations. It is to be understood that suchdirections and orientations are merely exemplary and for aiding inconcise description, but in no way limiting as to how devices and/orstructures may be disposed or formed.

With reference to FIG. 1, in one exemplary embodiment, an exemplarylayout 100 of devices under test (DUTs) is fabricated in an area on asemiconductor wafer. In the present exemplary embodiment, layout 100includes a DUT array 102 arranged in rows and columns. Although FIG. 1depicts 32 DUTs arranged in four rows and eight columns, it should berecognized that DUT array 102 can include any number of DUTs arranged inany number of rows and columns, including a single row or column.

Layout 100 also includes a pad set 104 formed adjacent to DUT array 102.In particular, in the present exemplary embodiment, pad set 104 includesa gate sense pad 106, a gate force pad 108, a source pad 110, and adrain pad 112. Each DUT in DUT array 102 is connected to gate sense pad106, gate force pad 108, source pad 110, and drain pad 112 of pad set104. As described in greater detail below, layout 100 can be formedwithout gate sense pad 106. Thus, pad set 104 can include only gateforce pad 108, source pad 110, and drain pad 112.

In the present exemplary embodiment, pad set 104 is formed laterallyadjacent to DUT array 102. Layout 100 can be formed in an area on awafer using a 2 metal layer front end-of-line (FEOL) short flow process.It should be recognized, however, that layout 100 can be formed usingvarious processes.

After layout 100 has been formed, each DUT in DUT array 102 iselectrically tested on the wafer using a wafer tester. In particular, inthe present exemplary embodiment, probes on the wafer tester contactgate sense pad 106, gate force pad 108, source pad 110, and drain pad112, then test each DUT in DUT array 102 individually in series. Asnoted above, layout 100 can be formed without gate sense pad 106, inwhich case, probes on the wafer tester contact gate force pad 108,source pad 110, and drain pad 112, then test each DUT in DUT array 102individually in series. In the present exemplary embodiment, the DUTs inDUT array 102 are sequentially tested. It should be recognized, however,that the DUTs in DUT array 102 can be tested individually in series inany desired order.

With reference to FIGS. 2-A and 2-B, in another exemplary embodiment, anexemplary layout 200 of DUTS is formed with pad set 104 formed adjacentto DUT array 102. In the present exemplary embodiment, layout 200includes pad array 104 formed vertically adjacent, above, DUT array 102.In particular, as depicted in FIG. 2-B, DUT array 102 is formed in onelayer on a wafer. Pad array 104 is formed in another layer on the waferstacked above the layer in which DUT array 102 was formed. As alsodepicted in FIG. 2-B, any number of metal layers 202 can be formedbetween the layers in which DUT array 102 and pad array 104 are formedto interconnect the DUTs in DUT array 102 and gate sense pad 106, gateforce pad 108, source pad 110, and drain pad 112 in pad array 104.

As also depicted in FIG. 2-B, in the present exemplary embodiment, gatesense pad 106, gate force pad 108, source pad 110, and drain pad 112include holes 204 that align over the DUTs in DUT array 102. Holes 204are sized to be larger than the DUTs in DUT array 102 to prevent randomcovering of DUTs in DUT array 102, which can cause matching andmeasurement errors. It should be recognized that metal layer 202 canalso be routed to prevent random covering of DUTs in DUT array 102.

FIG. 3 depicts an exemplary addressing and routing scheme for DUT array102. In the present exemplary embodiment, DUT array 102 includes 32 DUTssequentially addressed from the bottom left corner of DUT array 102 tothe upper right corner of DUT array 102. It should be recognized,however, that various addressing schemes may be used.

A row decoder 302 and a column decoder 304 can be used to individuallyaddress each DUT in DUT array 102. In the present exemplary embodiment,each DUT in DUT array 102 is tested using row decoder 302, columndecoder 304 to individually address each DUT in DUT array 102. Forexample, row decoder 302 and column decoder 304 can be used to firstaddress DUT (0) in DUT array 102. Pad array 104 can then be used to testDUT (0). Row decoder 302 and column decoder 304 can then be used toaddress DUT (1) in DUT array 102. Pad array 104 can then be used to testDUT (1). In this manner, DUTs (2)-(31) can be individually addressedusing row decoder 302 and column decoder 304, and then tested using padarray 104. Although the DUTs in DUT array 102 are sequentially addressedand tested in this example, it should be recognized that the DUTs can beaddressed and tested in any desired order.

FIG. 4 depicts an individual DUT 402 connected to source pad 110, drainpad 112, gate force pad 108, and gate sense pad 106. For the sake ofexample, DUT 402 is depicted as an NMOS transistor. It should berecognized, however, that DUT 402 can be various types of devices.

FIG. 4 depicts the source and drain of DUT 402 connected to source pad110 and drain pad 112, respectively, through tree-routed structures,which will be described in greater detail below. In the presentexemplary embodiment, the sources of all the DUTs in a particular DUTarray are connected in parallel to source pad 110 through a source treerouting structure, which will be described in greater detail below.Additionally, the drains of all the DUTs in a particular DUT array areconnected in parallel to drain pad 112 through a drain tree routingstructure, which will be described in greater detail below. Thus, duringelectrical testing, probes in contact with source pad 110 and drain pad112 can send and receive signals to and from all the DUTs in a DUT arrayat one time in parallel.

FIG. 4 also depicts the gate of DUT 402 connected to gate force pad 108and gate sense pad 106 through a selection circuit 400. In the presentexemplary embodiment, the gates of all the DUTs in a particular DUTarray are connected to gate force pad 108 and gate sense pad 106 throughselection circuit 400. Thus, during electrical testing, probes incontact with gate force pad 108 and gate sense pad 106 are connected toone DUT in a DUT array at a time through selection circuit 400. Each DUTin the DUT array is then selected for testing. As noted above, the gatesense pad 106 can be eliminated in some applications, such as when thegate leakage is negligible.

To test each DUT in a DUT array, selection circuit 400 is used to selecteach DUT addressed by row and column selection signals. As depicted inFIG. 4, selection circuit 400 includes selection logic 406 that receivesa row selection signal and a column selection signal. Thus, selectioncircuit 400 connects the gate of a particular DUT in the DUT array tothe gate force pad 108 and gate sense pad 106 to test the particularDUT. As also depicted in FIG. 4, the gate of DUT 402 is also connectedto a pull-down transistor 404 that keeps DUT 402 turned off when it isunselected. Note, depending on the polarity of DUT 402, a pull-uptransistor may be used instead.

In the present exemplary embodiment, selection circuit 400 also includesa mode to turn off all DUTs in a DUT array to measure an off conditionof the DUTs in the DUT array. To invoke this mode, a global enablesignal can be connected to control column decoder 304 (FIG. 3). Forexample, when a global enable pin is tied to ground, all the DUTs areturned off by forcing the output of column decoder 304 (FIG. 3) to zero.An off condition current (I_(off)) measurement can then be obtained forthe DUTs in the DUT array.

FIG. 5-A depicts an exemplary routing connection for DUT 402. Asdepicted in FIG. 5-A, DUT 402 is disposed within a cell 502. In thepresent exemplary embodiment, a first L-shaped routing structure 504 isdisposed at a first corner of cell 502. As depicted in FIG. 5-A, firstL-shaped routing structure 504 is connected to the drain of DUT 402. Asecond L-shaped routing structure 506 is disposed at a second corner ofcell 502. As depicted in FIG. 5-A, second L-shaped routing structure 506is connected to the source of DUT 402. A third L-shaped routingstructure 508 is disposed at a third corner of cell 502. As depicted inFIG. 5-A, third L-shaped routing structure 508 is connected to the gateof DUT 402. A fourth L-shaped routing structure 510 is disposed at afourth corner of cell 502. As depicted in FIG. 5, fourth L-shapedrouting structure 510 is connected to the well of DUT 402. As depictedin FIG. 5-B, DUT 402 can be rotated 90 degrees while using the samerouting connections.

FIG. 6 depicts an exemplary tree routing structure for connectingtogether in parallel drains and sources of multiple DUTs in a DUT array.In the present exemplary embodiment, the drains of multiple DUTs areconnected together in parallel using a drain tree routing structure 602,and the sources of multiple DUTs are connected together in parallelusing a source tree routing structure 604.

As depicted in FIG. 6, the drains of two adjacent DUTs are connectedtogether in parallel using one branch of drain tree routing structure602. For example, assume the drain of DUT 402(0) is connected toL-shaped routing structure 504(0) disposed at a corner of cell 502(0),and the drain of DUT 402(1) is connected to L-shaped routing structure504(1) disposed at a corner of cell 502(1). As depicted in FIG. 6, abranch 604(0) in a first hierarchy of drain tree routing structure 602connects together in parallel the drains of DUT 402(0) and DUT 402(1).In particular, branch 604(0) includes a segment 606(0) connected toL-shaped routing structure 504(0) and a segment 606(1) connected toL-shaped routing structure 504(1). In the present exemplary embodiment,segments 606(0) and 606(1) of branch 604(0) are electrically balanced.For example, the dimensions and electrical characteristics of segments606(0) and 606(1) can be made to be the same. In a similar manner,another branch 604(1) in the first hierarchy of drain tree routingstructure 602 connects together in parallel the drains of DUT 402(2) andDUT 402(3).

As depicted in FIG. 6, a branch 608(0) in the second hierarchy of draintree routing structure 602 connects together in parallel branches 604(0)and 604(1) to connect together in parallel the drains of DUTs 402(0),402(1), 402(2), and 402(3). In particular, branch 608(0) includes asegment 610(0) connected to branch 604(0) and a segment 610(1) connectedto branch 604(1). In the present exemplary embodiment, segments 610(0)and 610(1) are electrically balanced. For example, the dimensions andelectrical characteristics of segments 610(0) and 610(1) can be made tobe the same. In this manner, the drains of any number of DUTs can beconnected together in parallel using an appropriate number of branchesand hierarchies of drain tree routing structure 602.

As depicted in FIG. 6, the sources of two adjacent DUTs are connectedtogether in parallel using one branch of source tree routing structure604. For example, assume the source of DUT 402(0) is connected toL-shaped routing structure 506(0) disposed at a corner of cell 502(0),and the source of DUT 402(1) is connected to L-shaped routing structure506(1) disposed at a corner of cell 502(1). As depicted in FIG. 6, abranch 612(0) in a first hierarchy of source tree routing structure 604connects together in parallel the sources of DUT 402(0) and DUT 402(1).In particular, branch 612(0) includes a segment 614(0) connected toL-shaped routing structure 506(0) and a segment 614(1) connected toL-shaped routing structure 506(1). In the present exemplary embodiment,segments 614(0) and 614(1) of branch 612(0) are electrically balanced.For example, the dimensions and electrical characteristics of segments614(0) and 614(1) can be made to be the same. In a similar manner,another branch 612(1) in the first hierarchy of source tree routingstructure 604 connects together in parallel the sources of DUT 402(2)and DUT 402(3).

As depicted in FIG. 6, a branch 616(0) in the second hierarchy of sourcetree routing structure 604 connects together in parallel branches 612(0)and 612(1) to connect together in parallel the sources of DUTs 402(0),402(1), 402(2), and 402(3). In particular, branch 616(0) includes asegment 618(0) connected to branch 612(0) and a segment 618(1) connectedto branch 612(1). In the present exemplary embodiment, segments 618(0)and 618(1) are electrically balanced. For example, the dimensions andelectrical characteristics of segments 618(0) and 618(1) can be made tobe the same. In this manner, the sources of any number of DUTs can beconnected together in parallel using an appropriate number of branchesand hierarchies of source tree routing structure 604.

Thus, in the present exemplary embodiment, the drains of each DUT in arow of DUTs in a DUT array are connected together in parallel in a firsthierarchy of drain tree routing structure 602. Similarly, the sources ofeach DUT in a row of DUTs in a DUT array are connected together inparallel in a first hierarchy of source tree routing structure 604.

FIG. 7 depicts rows of DUTs stacked in a DUT array. As depicted in FIG.7, drain tree routing structures 602 of multiple rows of DUTs areconnected together in parallel into a vertical drain tree 702 on oneside. Source tree routing structures 604 of multiple rows of DUTs areconnected together in parallel into a vertical source tree 704 onanother side. In FIG. 7, vertical drain tree 702 is depicted as being onthe left side, and vertical source tree 704 is depicted as being on theright side. As noted above, it should be recognized that theseorientations are relative, and that location of vertical drain tree 702and vertical source tree 704 can be switched.

FIG. 7 also depicts routing lines 706 running vertically between columnsof DUTS in a DUT array. In the present embodiment, routing lines 706 cancarry power supply, gate force, gate sense, and selection signals.

With reference to FIG. 8, in another exemplary embodiment, an exemplarypad frame 800 having a pad set 802 of pads for control logic disposedbetween multiple DUT arrays is fabricated. In the present exemplaryembodiment, pad frame 800 includes a superset 804 of five pad sets 104for five DUT arrays 102 disposed on one side of pad set 802, and asuperset 806 of five pad sets 104 for five DUT arrays disposed onanother side of pad set 802.

In the present exemplary embodiment, the DUTs of DUT arrayscorresponding to supersets 804 and 806 are different types of DUTsrepresenting two types of experiments to be performed. For example, theDUTs of DUT arrays corresponding to superset 804 are NMOS-type DUTs,while the DUTS of DUT arrays corresponding to superset 806 are PMOS-typeDUTs. It should be recognized that supersets 804 and 806 can correspondto any number of DUT arrays 102 with any number of different types ofDUTs.

As depicted in FIG. 8, pad set 802 and supersets 804 and 806 can bearranged linearly. In the present exemplary embodiment, pad frame 800has a height 808 of approximately 4 millimeters and a width 810 of about60 microns. It should be recognized, however, that pad frame 800 canhave various dimensions.

In the present exemplary embodiment, pad frame 800 is formed in a scribeline between IC dice on a wafer. Pad frame 800 and the IC dice areformed on the wafer using an IC fabrication line. After the pad frame800 and IC dice are formed on the wafer, the DUTs in the DUT arrays ofpad frame 800 in the scribe line are tested. After the DUTs are tested,the IC dice are diced along scribe lines into IC chips. The IC chips arethen packaged. It should be recognized, however, that pad frame 800 canbe formed in any area on a wafer.

FIG. 9 depicts a portion of pad frame 800 in greater detail. Inparticular, FIG. 9 depicts pad set 802 having 8 pads disposed betweenone pad set 104 on one side and another pad set 104 on another side. Asalso depicted in FIG. 9, pad set 104 includes 4 pads, and each padhaving 8 DUTs disposed below the pad. Thus, each pad set 104 is disposedabove 32 DUTs.

FIG. 10 depicts a portion of pad frame 800 in cross section. As depictedin FIG. 10, pads 1002 of pad frame 800 are formed above DUT arrays 102and control logic 1004. In particular, as depicted in FIG. 10, DUTarrays 102 and control logic 1004 are formed in one layer on a wafer.Pads 1002 are formed in another layer on the wafer above the layer inwhich DUT arrays 102 and control logic 1004 was formed. As also depictedin FIG. 10, any number of metal layers 202 can be formed between thelayer in which DUT array 102 and control logic 1004 and the layer inwhich pads 1002 are formed to interconnect the DUTs in DUT arrays 102,control logic 1004, and pads 1002.

FIG. 11 depicts an exemplary pad mapping for pad frame 800. In thepresent exemplary embodiment, pad frame 800 includes 50 pads. Asdepicted in FIG. 11, pads 22-29 are mapped to provide power and controlsignals to the DUT arrays in pad frame 800. Pads 18-21 correspond to apad set for a first DUT array. Pads 14-17 correspond to a pad set for asecond DUT array. Pads 10-13 correspond to a pad set for a third DUTarray. Pads 6-9 correspond to a pad set for a fourth DUT array. Pads 2-5corresponds to a pad set for a fifth DUT array. Pads 30-33 correspond toa pad set for a sixth DUT array. Pads 34-37 corresponds to a pad set fora seventh DUT array. Pads 38-41 correspond to a pad set for an eight DUTarray. Pads 42-45 correspond to a pad set for a ninth DUT array. Pads46-49 correspond to a tenth DUT array. As noted above, in the presentexemplary embodiment, the first-fifth DUT arrays (pads 2-21 of pad frame800) are used for NMOS DUTs, while the sixth-tenth DUT arrays (pads30-49 of pad frame 800) are used for PMOS DUTs.

With reference to FIG. 10, control logic 1004 is configured to test eachDUT in a DUT array individually in series. In the present exemplaryembodiment, control logic 1004 is configured to test all the DUT arrays102 of pad frame 800 in parallel. Thus, ten DUTs (one DUT from each ofthe first-tenth DUT arrays of pad frame 800) are tested at one time inparallel. Additionally, in the present exemplary embodiment, DUTs in thesame array location in each of the first-tenth DUT arrays of pad frame800 are tested at one time.

For example, assume that DUTs in each of the first-tenth DUT arrays ofpad frame 800 are arranged and addressed in the manner depicted in FIG.3. Thus, in the present exemplary embodiment, with reference to FIG. 3,DUTs (0) in each of the first-tenth DUT arrays of pad frame 800 (FIG.10) are tested at one time in parallel. After DUTs (0) are tested, DUTs(1) in each of the first-tenth DUT arrays of pad frame 800 (FIG. 10) arethen tested at one time in parallel. As noted above, it should berecognized that the DUTs in the DUT arrays of pad frame 800 (FIG. 10)can be tested individually in series in any desired order.

With reference again to FIG. 10, in the present exemplary embodiment,pad 1 and pad 50 of pad frame 800 are used as calibration pads used tomeasure source and drain resistance. In particular, with reference toFIG. 4, the source resistance can be measured at measurement point 408,and the drain resistance can be measured at measurement point 410. Withreference to FIG. 11, it should be recognized that pads 1 and pad 50 canbe left as non-functional pads.

With reference to FIG. 10, in the present exemplary embodiment, controllogic 1004 can include a portion of selection circuit 400 (FIG. 4) toselect individual DUTs in DUT array 102 for testing. In particular,logic 1004 includes the global portion of selection circuit 400 (FIG.4). With reference to FIG. 7, the local portion of selection circuit 400(FIG. 4) are disposed in local logic 708 disposed adjacent to each DUT.

Although exemplary embodiments have been described, variousmodifications can be made without departing from the spirit and/or scopeof the present invention. Therefore, the present invention should not beconstrued as being limited to the specific forms shown in the drawingsand described above.

1. A layout for devices under test formed on a semiconductor wafer foruse in wafer testing, the layout comprising: a first array of devicesunder test; a first pad set formed adjacent to the first array, thefirst pad set including a gate force pad, a source pad, and a drain pad,wherein each of the devices under test in the first array is connectedin parallel to the drain pad of the first pad set; a source tree routingstructure connected to a source of each device under test in the firstarray, wherein the source tree connects the devices under test in thefirst array in parallel to the source pad, and wherein the source treerouting structure comprises: a first hierarchy of branches, each branchof the first hierarchy having a pair of segments connected to sources oftwo devices under test in the first array, wherein the pair of segmentsis electrically balanced; and a second hierarchy of branches, eachbranch of the second hierarchy having a pair of segments connected totwo branches of the first hierarchy; and a selection circuit connectedto each of the devices under test in the first array and the gate forcepad, wherein the selection circuit is configured to selectively connecteach of the devices under test in the first array to the gate force pad.2. The layout of claim 1, wherein the source tree routing structurecomprises: a first branch at the first hierarchy of the source treerouting structure, wherein the first branch includes a first segmentconnected to the source of a first device under test and a secondsegment connected to the source of a second device under test, andwherein the first device under test is adjacent to the second deviceunder test.
 3. The layout of claim 2, wherein the drain tree routingstructure comprises: a second branch at the first hierarchy of thesource tree routing structure, wherein the second branch includes afirst segment connected to the source of a third device under test and asecond segment connected to the source of a fourth device under test,wherein the third device under test is adjacent to the fourth deviceunder test.
 4. The layout of claim 3, wherein the drain tree routingstructure comprises: a third branch at the second hierarchy of thesource tree routing structure, wherein the third branch includes firstsegment connected to the first branch and a second segment connected tothe second branch, wherein the first branch is adjacent to the secondbranch, and wherein the first and second segments of the third branchare electrically balanced.
 5. The layout of claim 4, wherein the first,second, third, and fourth devices under test are disposed within a rowof the first array.
 6. The layout of claim 1, wherein a device undertest in the first array is formed within a cell, and further comprising:an L-shaped routing structure disposed at a corner of the cell, whereinthe L-shaped routing structure is connected to the source and one of thesegments of a branch of the first hierarchy of the source tree routingstructure.
 7. The layout of claim 1, further comprising: a drain treerouting structure connected to a drain of each device under test in thefirst array, wherein the drain tree connects the devices under test inthe first array in parallel to the drain pad, and wherein the drain treerouting structure comprises: a first hierarchy of branches, each branchof the first hierarchy having a pair of segments connected to drains oftwo devices under test in the first array, wherein the pair of segmentsis electrically balanced; and a second hierarchy of branches, eachbranch of the second hierarchy having a pair of segments connected totwo branches of the first hierarchy; and
 8. The layout of claim 7,wherein the drain tree routing structure comprises: a first branch atthe first hierarchy of the drain tree routing structure, wherein thefirst branch includes a first segment connected to the drain of thefirst device under test and a second segment connected to the drain ofthe second device under test; a second branch at the first hierarchy ofthe drain tree routing structure, wherein the second branch includes afirst segment connected to the drain of the third device under test andthe second segment connected to the drain of a fourth device under test;and a third branch at a second hierarchy of the drain tree routingstructure, wherein the third branch includes first segment connected tothe first branch and a second segment connected to the second branch,wherein the first branch is adjacent to the second branch, and whereinthe first and second segments of the third branch are electricallybalanced.
 9. The layout of claim 8, wherein the first, second, third,and fourth devices under test are disposed within a row of the firstarray.
 10. The layout of claim 7, wherein a device under test in thefirst array is formed within a cell, and further comprising: a firstL-shaped routing structure disposed at a first corner of the cell,wherein the first L-shaped routing structure is connected to the sourceof the device under test and one of the segments of a branch of thefirst hierarchy of the source tree routing structure; and a secondL-shaped routing structure disposed at a second corner of the cell,wherein the second L-shaped routing structure is connected to the drainof the device under test and one of the segments of a branch of thefirst hierarchy of the drain tree routing structure.
 11. A layout fordevices under test formed on a semiconductor wafer for use in wafertesting, the layout comprising: a first array of devices under test; afirst pad set formed adjacent to the first array, the first pad setincluding a gate force pad, a source pad, and a drain pad, wherein eachof the devices under test in the first array is connected in parallel tothe source pad of the first pad set; a drain tree routing structureconnected to a drain of each device under test in the first array,wherein the drain tree connects the devices under test in the firstarray in parallel to the drain pad, and wherein the drain tree routingstructure comprises: a first hierarchy of branches, each branch of thefirst hierarchy having a pair of segments connected to drains of twodevices under test in the first array, wherein the pair of segments iselectrically balanced; and a second hierarchy of branches, each branchof the second hierarchy having a pair of segments connected to twobranches of the first hierarchy; and a selection circuit connected toeach of the devices under test in the first array and the gate forcepad, wherein the selection circuit is configured to selectively connecteach of the devices under test in the first array to the gate force pad.12. The layout of claim 11, wherein the drain tree routing structurecomprises: a first branch at the first hierarchy of the drain treerouting structure, wherein the first branch includes a first segmentconnected to the drain of a first device under test and a second segmentconnected to the drain of a second device under test, and wherein thefirst device under test is adjacent to the second device under test. 13.The layout of claim 12, wherein the drain tree routing structurecomprises: a second branch at the first hierarchy of the drain treerouting structure, wherein the second branch includes a first segmentconnected to the drain of a third device under test and a second segmentconnected to the drain of a fourth device under test, wherein the thirddevice under test is adjacent to the fourth device under test.
 14. Thelayout of claim 13, wherein the drain tree routing structure comprises:a third branch at the second hierarchy of the drain tree routingstructure, wherein the third branch includes first segment connected tothe first branch and a second segment connected to the second branch,wherein the first branch is adjacent to the second branch, and whereinthe first and second segments of the third branch are electricallybalanced.
 15. The layout of claim 14, wherein the first, second, third,and fourth devices under test are disposed within a row of the firstarray.
 16. The layout of claim 11, wherein a device under test in thefirst array is formed within a cell, and further comprising: an L-shapedrouting structure disposed at a corner of the cell, wherein the L-shapedrouting structure is connected to the drain and one of the segments of abranch of the first hierarchy of the drain tree routing structure.
 17. Amethod of forming a layout for devices under test formed on asemiconductor wafer for use in wafer testing, the method comprising:forming a first array of devices under test; forming a first pad setformed adjacent to the first array, the first pad set including a gateforce pad, a source pad, and a drain pad, wherein each of the devicesunder test in the first array is connected in parallel to the drain padof the first pad set; forming a source tree routing structure connectedto a source of each device under test in the first array, wherein thesource tree connects the devices under test in the first array inparallel to the source pad, and wherein the source tree routingstructure comprises: a first hierarchy of branches, each branch of thefirst hierarchy having a pair of segments connected to sources of twodevices under test in the first array, wherein the pair of segments iselectrically balanced; and a second hierarchy of branches, each branchof the second hierarchy having a pair of segments connected to twobranches of the first hierarchy; and forming a selection circuitconnected to each of the devices under test in the first array and thegate force pad, wherein the selection circuit is configured toselectively connect each of the devices under test in the first array tothe gate force pad.
 18. A method of forming a layout for devices undertest formed on a semiconductor wafer for use in wafer testing, themethod comprising: forming a first array of devices under test; forminga first pad set formed adjacent to the first array, the first pad setincluding a gate force pad, a source pad, and a drain pad, wherein eachof the devices under test in the first array is connected in parallel tothe source pad of the first pad set; forming a drain tree routingstructure connected to a drain of each device under test in the firstarray, wherein the drain tree connects the devices under test in thefirst array in parallel to the drain pad, and wherein the drain treerouting structure comprises: a first hierarchy of branches, each branchof the first hierarchy having a pair of segments connected to drains oftwo devices under test in the first array, wherein the pair of segmentsis electrically balanced; and a second hierarchy of branches, eachbranch of the second hierarchy having a pair of segments connected totwo branches of the first hierarchy; and forming a selection circuitconnected to each of the devices under test in the first array and thegate force pad, wherein the selection circuit is configured toselectively connect each of the devices under test in the first array tothe gate force pad.